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| 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 SST30VR041 / 0434Mb Mask ROM (x8) + 1Mb / 256Kb SRAM (x8) Combo Data Sheet FEATURES: * ROM + SRAM ROM/RAM Combo - SST30VR041: 512K x8 ROM + 128K x8 SRAM - SST30VR043: 512K x8 ROM + 32K x8 SRAM * ROM/RAM combo on a monolithic chip * Equivalent ComboMemory (Flash + SRAM): SST31LF041A for code development and pre-production * Wide Operating Voltage Range: 2.7-3.3V * Chip Access Time - SST30VR041 70 ns and 150 ns - SST30VR043 150 ns * Low Power Dissipation: - Standby: 1.0 W (Typical) - Operating: 3.0 mW (Typical) * Fully Static Operation - No clock or refresh required * Three-state Outputs * Packages Available - 32-lead TSOP (8mm x14mm) PRODUCT DESCRIPTION The SST30VR041/043 are ROM/RAM combo chips consisting of 4 Mbit Read-Only Memory (ROM) organized as 512 KByte and a Static Random Access Memory (SRAM) organized as either 128 or 32 KByte. Output Enable Input (OE#) is pin-shared with RAMCS# (RAM Enable Input) signal in order to maintain the standard 32-lead TSOP package. The device is fabricated using SST's advanced CMOS low power process technology. The SST30VR041/043 have an output enable input for precise control of the data outputs. It also has two (2) separate chip enable inputs for selection of either SRAM or ROM and for minimizing current drain during power-down mode. The SST30VR041/043 is particularly well suited for use in low voltage (2.7-3.3V) supplies such as pagers, organizers and other handheld applications. FUNCTIONAL BLOCK DIAGRAM RAMCS# ROMCS# OE#/RAMCS# WE# Control Circuit OE# WE# Data Buffer RAM Address Buffer DQ7-DQ0 ROMCS# OE# AMS-A0 ROM Note: AMS = Most Significant Address 381 ILL B1.2 (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 1 The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. ComboMemory is a trademark of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet A11 A9 A8 A13 A14 A17 WE# VDD A18 A16 A15 A12 A7 A6 A5 A4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Standard Pinout Top View Die Up 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 381 ILL F01.0 OE#/RAMCS# A10 ROMCS# DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3 FIGURE 1: PIN ASSIGNMENTS FOR 32-LEAD TSOP TABLE 1: PIN DESCRIPTION Symbol AMS1-A0 Pin Name Address Inputs: ROM: AMS = A18 RAM: AMS = A16 for SST30VR041 A14 for SST30VR043 WE# OE#/RAMCS# ROMCS# DQ7-DQ0 VDD VSS Write Enable Input Output Enable/RAM Enable Input ROM Enable Input Data Input/Output Power Supply Ground T1.3 381 1. AMS = Most significant address (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 2 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20C to +85C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Voltage on Any Pin Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Soldering Temperature (10 Seconds Lead Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C OPERATING RANGE Range Commercial Extended Ambient Temp 0C to +70C VDD 2.7-3.3V 2.7-3.3V -20C to +85C OF AC CONDITIONS TEST Input Pulse Level . . . . . . . . . . . . . . . . . . . . 0-VDD Input & Output Timing Reference Levels . . . VDD/2 Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . . CL = 30 pF for 70 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . . CL = 100 pF for 150 ns (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 3 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet TABLE 2: RECOMMENDED DC OPERATING CONDITIONS Symbol VDD VSS VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min 2.7 0 2.4 -0.3 Max 3.3 0 VDD + 0.5 0.3 Units V V V V T2.0 381 TABLE 3: DC OPERATING CHARACTERISTICS VDD = 2.7-3.3V Symbol IDD1 IDD2 ISB ILI ILO VOL VOH Parameter ROM Operating Supply Current SRAM Operating Supply Current Standby VDD Current Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage 2.2 -1 -1 Min Max 4.0+1.1(f)1 2.5+1(f)1 10 1 1 0.4 Units mA mA A A A V V Test Conditions ROMCS#=VIL, RAMCS#=VIH, VIN=VIH or VIL, II/O=Opens ROMCS#=VIH, RAMCS#=VIL, II/O=Opens ROMCS# VDD-0.2V, RAMCS# VDD-0.2V VIN VDD-0.2V or VIN 0.2V VIN=VSS to VDD ROMCS#=RAMCS#=VIH or OE#=VIH or WE#=VIL, VI/O=VSS to VDD IOL=1.0 mA IOH=-0.5 mA T3.5 381 1. f = Frequency of operation (MHz) = 1/cycle time TABLE 4: CAPACITANCE Parameter CI/O 1 (Ta = 25C, f=1 Mhz) Description I/O Pin Capacitance Input Capacitance Test Condition VI/O = 0V VIN = 0V Maximum 8 pF 6 pF T4.1 381 CIN1 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter. (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 4 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet VIHT INPUT VIT REFERENCE POINTS VOT OUTPUT VILT 381 ILL F07.0 AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are VIT (0.5 VDD) and VOT (0.5 VDD). Input rise and fall times (10% 90%) are <5 ns. Note: VIT - VINPUT Test VOT - VOUTPUT Test VIHT - VINPUT HIGH Test VILT - VINPUT LOW Test FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS TO TESTER TO DUT CL 381 ILL F08.0 FIGURE 3: A TEST LOAD EXAMPLE (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 5 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet AC CHARACTERISTICS I. ROM Operation TABLE 5: READ CYCLE TIMING PARAMETERS Symbol TRC TAA TCO TOE TLZ TOLZ THZ TOHZ TOH Parameter Read Cycle Time Address Access Time Chip Select to Output Output Enable to Valid Output Chip Select to Low-Z Output Output Enable to Low-Z Output Chip Disable to High-Z Output Output Disable to High-Z Output Output Hold from Address Change 10 0 0 25 25 15 VDD = 2.7-3.3V SST30VR041-70 Min 70 70 70 35 0 0 30 30 Max SST30VR041/043-150 Min 150 150 150 70 Max Units ns ns ns ns ns ns ns ns ns T5.2 381 TRC Address TAA TOH Data Out Previous Data Valid Data Valid 381 ILL F02.0 FIGURE 4: ROM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (ROMCS# = OE# = VIL) TRC Address TAA ROMCS# TCO TLZ(2) OE# TOE TOHZ(1) THZ(1,2) TOLZ High-Z Data Out Data Valid TOH 381 ILL F03.0 Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL. 2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device. FIGURE 5: ROM READ CYCLE TIMING DIAGRAM (ROMCS# & OE# CONTROLLED) (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 6 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet II. SRAM Operation (ROMCS# = VIH) TABLE 6: READ CYCLE TIMING PARAMETERS VDD = 2.7-3.3V SST30VR041-70 Symbol TRC TAA TCO TLZ THZ TOH Parameter Read Cycle Time Address Access Time Chip Select to Output Chip Select to Low-Z Output Chip Disable to High-Z Output Output Hold from Address Change 10 0 25 15 Min 70 70 70 0 30 Max SST30VR041/043-150 Min 150 150 150 Max Units ns ns ns ns ns ns T6.2 381 TABLE 7: WRITE CYCLE TIMING PARAMETERS VDD = 2.7-3.3V SST30VR041-70 Symbol TWC TCW TAW TAS TWP TWR TWHZ TDW TDH TOW Parameter Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up Time Write Pulse Width Write Recovery Time Write to Output High-Z Data to Write Time Overlap Data Hold from Write Time End Write to Output Low-Z 30 0 0 Min 70 60 60 0 60 0 30 60 0 10 Max SST30VR041/043-150 Min 150 120 120 0 120 0 60 Max Units ns ns ns ns ns ns ns ns ns ns T7.2 381 (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 7 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet TRC Address TAA TOH Data Out Previous Data Valid Data Valid 381 ILL F04.0 FIGURE 6: SRAM READ CYCLE TIMING DIAGRAM (ADDRESS CONTROLLED) (OE#/RAMCS# = VIL, WE# = VIH) TRC Address TAA OE#/RAMCS# TCO TLZ(2) High-Z Data Out Data Valid 381 ILL F05.0 THZ(1,2) TOH Notes: 1. THZ and TOHZ are defined as the time at which the outputs achieve the open circuit condition and are referenced to the VOH or VOL. 2. At any given temperature and voltage condition THZ(max) is less than TLZ(min) both for a given device and from device to device. 3. WE# is high for Read cycle. FIGURE 7: SRAM READ CYCLE TIMING DIAGRAM (OE#/RAMCS# CONTROLLED) (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 8 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet TWC Address TAW TCW(2) OE#/RAMCS# TAS(3) WE# TDW High-Z Data In TWHZ(5) Data Out High-Z (6) Data Valid TOW TDH TWP(1) TOH TWR(4) (7) (8) 381 ILL F06.0 Notes: 1. A write occurs during the overlap (TWP) of a low RAMCS# and low WE#. A write begins at the latest transition among RAMCS# going low and WE# going low: A write end at the earliest transition among RAMCS# going high and WE# going high, TWP is measured from the beginning of write to the end of write. 2. TCW is measured from the later of RAMCS# going low to the end of write. 3. TAS is measured from the address valid to the beginning of write. 4. TWR is measured from the end of write to the address change. 5. If RAMCS#, WE# are in the read mode during this period, the I/O pins are in the outputs Low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 6. If RAMCS# goes low simultaneously with WE# going low or after WE# going low, the outputs remain high impedance state. 7. DOUT is the same phase of the latest written data in this write cycle. 8. DOUT is the read data of new address 9. ROMCS# = VIH FIGURE 8: SRAM WRITE CYCLE TIMING DIAGRAM (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 9 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet TABLE 8: FUNCTIONAL DESCRIPTION/TRUTH TABLE Address Inputs X2 AMS3-A0 Only AMS4-A0 are valid ROMCS# VIH VIL VIL VIH VIH 1. 2. 3. 4. OE#/RAMCS#1 (Pin 32) VIH OE# (H) OE# (L) RAMCS# (L) RAMCS# (L) WE# X X X VIH VIL DQ7-DQ0 Z Z DOUT DOUT DIN Standby Output Floating ROM Read RAM Read RAM Write T8.4 381 OE# & RAMCS# are pin-shared X can be VIL or VIH, but no other value. For ROM: AMS = A18 for SST30VR041 and SST30VR043 For SRAM:AMS = A16 for SST30VR041, A18-A17 must be fixed to "VIL" or "VIH" AMS = A14 for SST30VR043, A18-A15 must be fixed to "VIL" or "VIH" (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 10 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet PRODUCT ORDERING INFORMATION Device SST30VR0xx Speed XXX Suffix1 X Suffix2 XX Package Modifier H = 32 leads Package Type W = TSOP (type 1, die up, 8mm x 14mm) Temperature Range C = Commercial = 0C to +70C E = Extended = -20C to +85C Read Access Speed 70 = 70 ns 150 = 150 ns Device Density 041 = 4 Mbit ROM + 1 Mbit SRAM 043 = 4 Mbit ROM + 256 Kbit SRAM Voltage Range V = 2.7-3.3V Device Family 30 = ROM/RAM Valid combinations for SST30VR041 SST30VR041-70-C-WH SST30VR041-150-C-WH SST30VR041-70-E-WH SST30VR041-150-E-WH Valid combinations for SST30VR043 SST30VR043-150-C-WH SST30VR043-150-E-WH Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 11 4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo SST30VR041 / SST30VR043 Data Sheet PACKAGING DIAGRAMS Pin # 1 Identifier 1.05 0.95 0.50 BSC 8.10 7.90 0.27 0.17 12.50 12.30 DETAIL 1.20 max. 0.70 0.50 14.20 13.80 0.15 0.05 0- 5 0.70 0.50 Note: 1. Complies with JEDEC publication 95 MO-142 BA dimensions, although some dimensions may be more stringent. 1mm 2. All linear dimensions are in millimeters (max/min). 3. Coplanarity: 0.1 mm 4. Maximum allowable mold flash is 0.15 mm at the package ends, and 0.25 mm between leads. 32-tsop-WH-7 32-LEAD THIN SMALL OUTLINE PACKAGE (TSOP) 8MM SST PACKAGE CODE: WH X 14MM Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.sst.com (c)2002 Silicon Storage Technology, Inc. S71134-02-000 2/02 381 12 |
Price & Availability of SST30VR043-150-C-WH
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